Method and circuits for synchronizing counters



Sept.

M. L. MBCKNIGHT METHOD ND'CIRCUITS FOR SYCHRONIZING COUNTERS Y Filed may 12, v1954 s sheets-shan 1 A Sept. 17, .1957

METHOD AND Filed May 12, V1954 M L MacKNlGl-rr 2,806,947 CIRCUITS FOR SYNCHROIIIZING COUNTERS 3 Sheets-Sheet 2 sept. 17, 1957 M. L MaQKNlGHT A2,806,947

METHOD AND CIRCUITS FOR sYNcHRoNIzING couNTERs Fi1ed May 12, 1954 3 sheets-sheet s 2,8%,9'47 Patented Sept. 17, 1957 METHOD AND CIRCUTS FOR SYNCRONIZING COUNTERS Merritt L. MacKnght, Manhattan Beach, Calif., assigner to Hughes Aircraft Company, Culver '-City, Calif., a corporation of Delaware Application May 12, 1954, serai Na. 429,281

1o Claims. (ci. 25a-27) This invention relates to a method and circuits for synchronizing counters, and more particularly toa method and circuits for initiating and maintaining synchronism between an electronic counter :circuit and synchronizing signals having a repetition period 'different from the free-running or natural period of the counter.

In many applications it is desirable to maintain synchronous operation of a counter with respect to a periodic cycle of countable events, each count being produced by the counter in response to a particular event of the cycle. As an example, in a digital computer an electronic counting circuit may be utilized to identify successive time intervals by counting timing or clockpulses which occur iat the beginning of each time interval. Thus, if a series of seven binary signals occurring during successive time intervals are employed to represent an infomation character, a scale-.of-seven counter may be utilized to identify each binary signal of the series by associating a particular count with each signal.

In the prior art the general technique for resetting a counter has been to instantaneously set all counter stages to a predetermined set of states representing an initial count. This resetting technique usually requires the application of a reset signal to each counter stage input circuit, as for example, in the reset circuit found in U. S. Patent Serial No. 2,568,918 entitled Reset Circuit for Electronic Counters by l. E. Grosdol, issued September 25, 1951. According to the reset technique of this patent signals are applied to one input circuit of all counter stages to inhibit the application of counting pulses, and other signals are simultaneously applied to the other input circuits of the counter stages in order to reset the stages to a set of stable states representing the initial count.

The instantaneous reset techniques of the prior art have been suitable for controlling a counter to count through an undetermined portion of its natural cycle, then to return instantaneously to the zero count state when a new cycle is to be commenced. These techniques have also been useful for maintaining synchronous operation of a counter at its free-running or natural period, the reset pulses being spaced by a number of counts equal to the natural count of the counter.

The primary disadvantage of the prior art lies in the fact that the methods required for the instantaneous reset are unnecessarily complicated where they are utilized in applications where an instantaneous reset is not required. This sort of complication results from the fact that the prior art technique does not fully utilize the initial resetting time which may be allowed in initiating the operation of a counter. Thus, no simpliication is achieved in the prior art resetting or synchronizing circuits by allowing a longer period of time for the resetting operation.

The significance of the disadvantage of the prior art technique becomes more readily apparent where the counter circuits without synchronization are very simply mechanized. ln this situation the introduction of the conventional resetting or synchronizing circuits may result in an almost double complexity in the gating circuits, as well as a considerable increase in the amount of loading upon the counter stages. An example of a typical situation which may occur is in the increase of cincuit complexity which results when counters of the type described in copending U. S. patent application Serial No. 327,131 for Binary-Coded Flip-Flop Counters, by Robert R. Johnson, tiled December 20, 1952, are reset and synchronized according to conventional techniques. It is evident from an analysis of the problem that if the synchronizing techniques of the prior art are utilized in conjunction with the type of counter described in the Johnson application, the yadvantages of the counter would be largely destroyed by the complexity of the means for controlling it.

The above and `other ydisadvantages of prior art reset circuits are obviated, according to the present invention, by allowing an initial synchronizing period during which the counter to be reset is caused to process with respect to applied synchronizing signals until one synchronizing signal coincides with a predetermined 'count of the freerunning or natural counting cycle. Procession is dened as the .coincidence of successive synchronizing signals with progressively dierent counts of the counter. After the precession period, the counter is maintained in synchronism with the synchronizing signals in the desired counting cycle which includes a number of counts equal to an altered counting cycle plus an integral multiple of the number of counts in the natural cycle.

As used herein, the term natural counting cycle and the term natural period of operation are each dened as the number of count signals to which the counter responds in order to complete a full operating cycle, in the absence of any applied synchronizing signals.

In its basic structural form the invention comprises a lirst gating circuit coupled to at least one flip-flop input circuit lof the counter to be controlled for applying synchronizing signals to the dip-flop input circuit in a manner such that the counter is actuated to precess until one synchronizing signal coincides with the predetermined count of the natural counting cycle. The synchronizing circuit also includes a second gating circuit which is coupled to at least one flip-nop input circuit, the second gating circuit being responsive to the one synchronizing signal which coincides with the predetermined count for actuating the counter to initiate an altered counting cycle; the number of counts in the altered cycle being 'less than the number of counts in the desired counting cycle by an integral multiple of the number of counts in the natural counting cycle.

An altered counting `cycle as herein referred to is one which results from the introduction of the synchronizing signal into the control function for at least one ilip-op :circuit and may in certain cases include only a single counting state indicating that the application of the synchronizing signal inhibits a change in the counter state.

The synchronizing pulse period is always the desired counting cycle period and must be different from the natural counting cycle period. The magnitude of the difference between the synchronizing period and the natural counting period determines the rate or manner of precession. Thus, in a specific form of the present invention, a natural scale-of-eight Johnson counter may be synchronized as a scale-of-nine counter. In this situation the counter will precess, from any random starting state, at the rate of one count position for each application of a synchronizing signal, until the predetermined count is located with initiates the altered counting cycle. The altered counting cycle in this case includes only one count since the counter is caused to lock on the predetermined count when the synchronizing signal is applied.

An important feature ofhthel scale-'of-m'ne counter is that only three flip-liep vstages are required where normallyV four are used. Thus, the synchronizing method of the present invention makes it possible to achieve counting; capacities of 21H-'1 ycounting states, where n is the number of. flip-hops. Such an arrangement does not-require additional structure'V since some sort of synchronizing meansis alwaysrequired in practical applications of counters.

The method of `synchronizingthe naturalscaleof-eight counter above may beconsidered. to bean mhibitmg Vtechniquewhere a particular count is heldfor an additionaltimeinterval. Itris-alsolpossible, according-to the presentinvention, to introduce alteredy counting-cycles by this embodiment the' synchronizing signalV is utilized tov introduce additional fiipop`gchangesinto V-thenorn'lalcounting sequence, resulting inthe'slippingroyer of-jcertain: naturalv countsv and the shorteningj o f the counting cycle by. one-count.4 While th'evspeciiic improvement of the inventionis'particularly useful inl connection with minimum-gatingv-,circuits-such as the Johnson counters it may also beutili'zed in' more omplicatedcounting systems Withappropriate modification.A Thus, a circuit-is described for synchronizing a conventional binaryV counter4V withV a: Very simple gating-circuit.V

Accordingly it is-an object of the invention-to provide av synchronizing circuitwhich is'simplyY mechanized due to the factlthatthe counter is--precessed during an initialV operating period.

AnotherV object ofl the invention is to provide a method andcircuit for synchronizing the operation ofV a counter circuits ina cycle including a number of counts different from the number orf-counts in its natural counting cycle.

A further objectofthe invention-is to provide a simple method-for Vsynchronizing a counter whereby a predetermined countis'locatedA during a first phase ofoperationland the counter is then actuated into an alteredv counting-cycle a second-phase of operation.Y

YA still further object of the invention is to synchronize the operation of a' counter, utilizing a synchronizing matrix which. is simply constructed and 'which minimizes the loadingupon the counter circuit.

Still another object of the invention is to provide a circuit for synchronizing a counter at aY desired' countV which diiers fromr its' naturalY count', utilizing precession'y to achieve initial synchronisrn withina few counting cycles; andi maintaining synchronism thereafter by altering the naturalcounting cycle. o f the counter spond' tothe desired count.

Yet a further object of the invention is' to provide means for synchronizing acounter at a counting'capacity ofhZn-F l, where n is the number of stages in the counter. vYet another object of the invention is to provide a method andl circuit for synchronizing a scale-of-eight counter` as aj scale-of-nine'counter.

VAn additional object ofV the invention is to provide' al circuit for synchronizing a scale-of-lS counter as a scaleof-l4v counter. Y Y

The novel features` which are believed to` be characteristic ofthe invention;` both as' toits organizationY and methodofoperation, together withi furtherobjects and advantages thereof, will be bettenunderstoodfrom the following Adescription considered' in connection' with the.

accompanying drawings in which severalembo'diments of the invention'arejillustrated by way of examples. It is `to be expressly understood, however, that thev drawings are for the'pvurposeV of illustration and description only, and are not intended as aV definition ofthe limitsY oftheinvention. 1

Fig. lV shows ai block Vdiagram of asynchronizing'ci'rcuit according to the present invention, the circuitbeing utilized to synchronize the operation of a counter inaccordance with the method of theinvention;

Fig. 2 is a schematic diagram of a synchronizing cu'- cuit for controlling a scale-of-eight Johnson counter to Y operate as a scale-of-nine counter in accordance with-the present invention;

Fig. 2a is a diagram illustrating the natural counting cycle and altered counting cyclesin the operationofthe embodiment of Fig. 2;

Fig. 3 isa schematic diagram of. a synchronizingc ir`.v cuit for controlling a scale-of-lS Johnson counter to operate as a scale-of-l4 counter;

Fig. 3a is a diagram illustrating the naturalcounting cycle andl altered counting` cycles inthe operation of the embodiment of Fig. 3; Y Fig. 4 is a schematic diagram of a synchronizing circuit for controlling a scale-of-lS Johnson counter to operate'as aAscale-of-ldcounter;

Fig. 4a is a diagram-,illustrating the naturalcounting cycle` and altered-counting cycles iri-th'elopera'tionfA of the` embodiment ofvFig.4; and

` signals-S coincides with the predetermined-starting-.state Fig. 5i is a schematic diagram of asynchronizing-circuit for controlling a conventional binary Ysca.le'-of16 counter to operate asascale-of-l7- counter.

VReferenceis now` made toFig. l whereinthere is `shownv a-syncluronizing-rnatrixl 100- according tothe presentinvention; synchronizing-matrixV 100 beingresponsive-to applied: synchronizing signals Sf to produce control-signals.- applied to at least oneinput ip-flop circuitl in al counter 200. The period betweensynchronizing signals- S is selected. sothat counter 20G-is actuated-to precess until the time-of application of oneofL the-synchronizing ofthercou'nter.

As indicated Vin-Fig. l countingcircuitfZ'fr includes aV counting control matrixVr Z110-for receiving and applying-a count-signal Cp toa plurality of Iflip-flops A; B1, N, where-N isthe number of-flip-ilops. Synchronizing matrix- 10Q/produces one or more control'signals which are applied through count control matrix 2'10'to at lleast one offiip-fiopsA N- and are eiective yto inhibit or introduce certainip-op changes and'V initiate certain a'l'-VV tered counting cycles vas vwill` be more fully understood- `from the detailed description which follows:

It isebelieved thatthe invention Will be best understood byy rst considering certain specific forms and'then developing a generic theory. Thus, reference is made toFig'; 2

A illustrating a specific form of synchronizing 'matrix .1D0-2j which' is utilizedrto control the operationV of a" counter -where'thesymbols lA, lB, and lC`representv l-setting nip-tiopinput signals and the symbols 0A, 0B', andjOC represent (l-setting flip-nop inputv signals. It is assumed,v as in the above-mentioned copending applicationtolohnson, that -ip-ops A, B, and Care conventionalip-ops i such that signals applied separate-ly to they l-settingand 0- setting Yinput circuits set the flip-flop t-o stablestatesrepresenting l and 0 respectively, and such thatV tiiesirnultaneous application of signals to both inputcir'cuits triggers the ip-fiop or changes its stable state. The dot (t)V in-thelogical equations represents the. logical and inf,

dicating that a` count pulse Cp is applied to the-corresponding input circuit only` when all' other input signals are l-representing signals. The bar `over a signal represents the complement. The natural counting cycle of counter 200-2 defined by these equations is indicated in Table I below.

Table I corresponds to Table Xl in the Johnson application, the particular counting sequence being numbered in column (5) of Table Xl. It will be noted, however, that the particular count number has no particular signicance since any desired count may be selected as the starting point. The specic manner in which the natural counting functions are derived will not be considered here since they do not form part of `the present invention, the Johnson application `therefore being incorporated herein by way rof reference.

In referring to Table I it will be noted that by inhibiting the change of ilip-op C from 0 to 1 after count 7, count 7 is thereby repeated, producing an altered counting cycle having one count. This change of iip-iiop C from O to l would also normally occur between the lirst and second counts, hence inhibiting the change will initiate another altered counting cycle commencing after the rst count. These effects may be represented dia- .grammatically as in Fig. 2a, from reference to which it may be noted that the natural counting cycle is designated vin solid lines with arrows indicating the direction of progression. The natural counting cycle is shown as including counts 1 through 8, corresponding to the sequence of 'Table 1.

.The `altered counting cycles which result from inhibiting the change of ip-flop C from 0 to 1 are illustrated by means of dotted lines, with arrows indicating lthe `direction of progression. The locking on count 7 is illustrated by a dotted loop which starts at 7 and returns directly thereto, and a progression .from count 1 to count 5 is shown as a dotted line connecting the numeral 1 to the numeral 5.

The inhibiting action referred to above may be accomplished by the application of a signal Sd, the complement of synchronizing signal S, to input circuit 1C of ip-op IC. The modied mechanization for the input circuits of flip-flop C then becomes:

The predetermined count state to lwhich the counter may be reset in accordance with the present invention must be a count state from which, upon coincidence of .a synchronizing signal S, an altered counting cycle is initiated. Thus, in the example shown, 'the predetermined ycount may be either count 1 or count 7. If the predetermined count is 7, the altered counting cycle which is produced includes only one count, namely, a repetition of count 7. Synchronous operation of the counter may therefore be maintained if the period of the synchronizing signals corresponds to 1, 9, 17, counts. If the predetermined count is count l, synchronous operation may be maintained if the period of the synchronizing signals corresponds to 5, 13, 2l, counts.

It is advantageous at this point to define an altered `counting cycle as a cycle which occurs between the application of a synchronizing signal and the return of the counter to the next count of its natural counting cycle. Thus, in the counting pattern illustrated in Fig. 2a, there G are two altered'counting cycles, Ione having one count (repetition of count 7), and the other having ve counts (counts 5, 6, 7, 8, and 1). It is now possible to state in equation form the relation between possible synchronizing periods, the natural counting cycle of the counter, and the various `altered counting cycles, as follows:

where Nc represents the natural count of the counter, Ac represents an altered count, K is `any positive integer including zero, and Dc represents the number of counts corresponding to the period -of the synchronizing signals.

Applying this general equation to the above example, the following equations apply:

Dc1=1, 9, 17, 25, Dc2=5, 13, 21, 29,

where Dc1 and Dc2 represent, respectively, two different sets of values from which the period of synchronizing signals S may be selected.

It will be noted that the counter :circuit of Fig. 2 could therefore be maintained in synchronous operation at any of the synchronizing periods indicated. According to Fig. 2 the synchronizing period is in fact equal to nine counts, hence the predetermined count is the seventh count. The full nine counts of the synchronizing period may therefore be identified by considering the presence or absence of lsignal S in order to distinguish between the first and second occurrences of the seventh count. The first occurrence of the seventh count, during which signal S is present, may be considered as the last count of the new cycle, and the second occurrence of the seventh count as the rst count of the new cycle.

In the event that it is desired to commence the counting cycle with a counter ystate which includes all 0s, this may be achieved by making a transformation in the structure of the counter circuit in accordance with the fundamental principles of Johnson counters, as described in the copending application. By complementing the state of ip-lop A throughout, the natural counting sequence will then be as shown in Table Il:

Table Il According to the above transformation the matrix functions for the counter become:

1C=oc=icp and the modied signals to be applied to iiip-iiop C in order to achieve the counting pattern of Fig. 2a would be the same as stated previously.

In synchronizing the operation of the counter circuit shown in Fig. 2 it is necessary not lonly to satisfy the requirements for maintaining synchronism once it is achieved, but it is also necessary to insure that proper precession will occur to provide the initial synchronism. lf the first synchronizing signal coincides with the second count successive signals will coincide with the 3rd, 4th, 5th, 6th, and 7th counts, respectively, thus requiring ve ing. nofoos. to nnain'ninnl. Synohronisni-l 4Sy.nohionsri,

Will ho attained rosaroioSs-of th'oonnifwith'iyhoh'he rst synchromzing signal coincides, and the' niaitimum procession time will Ybc. rivev synchronizing periods.

Thus.. fhnoironit o; Pi,"r 2. provides. 's ynohronons onorntion of, the oonntor, no fniallya scalo-sof" toonntor; as.,

' ion'oi horn tho Counter, and th. synohronizina ononit info onfronioly Sini.- ple,` thnsfrooniring. a niinininni, oi oironitoionaonts and resulting in minimum' loadingI of the counter stages. The, counting capacity of nine counts'is achieved With Vonly three ip-ops, thus providing a. totalI count of 2"-i-1 instead of the usual 2n, Where n isthe number of Hip-Hops in the counter. Y

As previously pointed out the counter circuit of Fig. 2 may be maintained synchronous operation at 1, 9, 17, 25 Counts, :or at 5., 13,. 2,1, '2.9 oonnts- .It iS nooossnryio Consider the Procession Phobien honorer, foreach desired synchronizing period. It the period selected is tive counts,V then a signal: S` will coincide with every ifth count vsigna-l Cp, and alsowith every 25th count signalCp. If'the first signal S Vcoincides with the rstY or fourth count the countervv'ill synchronize properly at tive counts. But ifY the iirst signal S coincides with the 7th, 2nd, 5th, 8th, 3rd, or 6th count, ,ther 1 synchrouism at 25 counts Will result, every 5th signalY S coinciding with the 7th count Vto produce an altered counting cycle hav- Ving one count and each group of four intervening signals S havingno'etect upon the natural counting cycle.

It is therefore apparent that if the desired` synchronizing period is a submultiple of anothernossible synchronizing period precession cannot be relied onto obtain the desired synchronism.V inthe converse situation where the desired synchronizing period is a multiple ofv another possible period the desired precession Amay be obtained.

' The methods of mechanizing synchronizing matrix 10Q-24 are not limited to the one shown in Fig, 2. For example, it is possible to inhibit the change of flip-hop C from l to O, thus providing a counting pattern entirely different from that shown in Fig. 2 a. Other counting patterns may be derived by inhibiting the change of iiipfiop A or flip-hop B from 0 to l, or from 1 to G. Furthermore, as will be pointed out in the ensuing discusa' SoHlo-offnino 'oonntor- The 'nioohanlzat sion it is possible to employ an active synchronizing control in lieu of an Vinhibiting signal, or to employ a corn-Y 'bination of both types of signals.

Reference is now made to Fig. 3Y illustrating a specific form ofY synchronizing matrix 100.-.3. which is'utilizedk to.

control the operation ofthe counter 200-3, normally having scale-of-lS operationunde'rlthecontrolY ofY a count control matrix V210-3, toV operate as la scale-of-l4 counter. The counter may be synchronized inrothler c ouutingcycles as Will be explained.V

Thematural counting function Vof counter u13 is described in copending U. S. patent application SerialV Number 373,558 for Shifting Register Counters, -by Robert R. Johnson, led August 171, 1953, and is specified by the equations:

of counter 20.0.-3 deiined by Vthese equations isr indicated iuTable III below.

2O' or signa employed in matrix. 10o-2, of nig. 2.. rhum running operation f into thestate L, as` for example' when the circuit is firstl accesos?.

Tabla 111.

Synoluonziny matrix, 1119-3. is n,isoolianizofl withy an ao.. tire synchronizing control. in. lion of: the inhibiting. typo.

14: (D+S-CI? With-this mechanizationv the counter circuit of Fig. 4 may be controlled for'sy'nchronous operation atV a; periodcorrosp'onnins'to 14 Counts- Reference is novy made to Fig. 3a which illustrates theV counting pattern which corresponds to the above mechanization `of the circuit of Fig'3. It Will be noted that the natural counting cycle includes counts' 1 through 1 5, inclusivgcorresponding tothe sequence of Table I II, andV also an unused count L, InV the natural or 'freercounter, if itV should ever fall1 energized, their it willremain in that state. The inclusip y of'the'actiye synchronizing Signal producesy four altere, counting cycles which are designated by means Vof dotted lines.

i One altered counting cycle causes the counter to atl- Vance/from count L to count lO. A second alteredV cycle causes count 8 to be followed by count 6. A third altered cycle causes count 1lV to be followed by count 4,

and a fourth alteredcycle causes count 12 to advance to count 14. l Y

. Based upon the above altered counting cyclesv the possible synchronizing periods for the circuit of Fig. 3 then are:

When synchronism is to be initiated at 14 counts the precession phase requires a of ten synchronizing periods, when the tirst synchronizing signal coincides either with the 71th or 1'() count.

For initiating synchronous operation at three counts, however, precession'cannotbe relied on. This may be demonstrated by dividing all ofthe counts of the natural cycle into Va rst set including counts l, 4, 7, 10, and 13; ay second set including counts 2, 5, 8, 1l, and 14); andl a third set including counts 3, 6, 9, l2, and l5.Y If the tirst synchronizing signal coincides with one' of thel counts in the first se`t then subsequent signals will coincide with other counts of that set, in the absence of an altered counting cycle. Similarly, ifvthe rst synchronizing signal were'tocoincide With'a count in the secondset or' inthe thirdset, subsequent counts would process Within the same set. l

It may be notedv that there is no altered counting cycle to lead the precessicn out o f the first set. But the predetermined count is in the second set of counts; therefore, proper synchronism vivould never be attained if'the rst synchronizing signal were to coincide with one of the counts of the irst set.

If the rst synchronizing signal were to coincide With one of the counts of the third set, precession would continue until count 12 was reached, and precession would then shift to the iirst set of counts. Thus again proper synchronism would not be attained.

The diiculty in initiating synchronism at three counts Would also exist if synchronism at 18 counts were attempted. It may therefore be stated as a general proposition that Whenever there is a common factor between the desired count and the natural count, there must be altered counting cycles which will lead the precession back to the particular set of counts in which the predetermined count is included, if synchronous operation is to be achieved.

Whereas only one specific mechanization has been illustrated in Fig. 3, it is apparent that synchronizing matrix 100-3 might be mechanized in many other Ways. Either inhibiting signals or active synchronizing signals might be applied to any of the p-flop input circuits of counter 200-3, thus providing a variety of mechanizations each of which would provide a different counting pattern.

Reference is now made to Fig. 4 illustrating a synchronizing matrix G-4 which is utilized to control the operation of a counter 200-4, normally having a scale-ofoperation under the control of a count control matrix 210-4, to operate as a scale-of-l counter.

The natural counting function and the mechanization of counter 200-4 are the same as counter 2041-3, described above in connection with Fig. 3. synchronizing matrix 100-4 provides the same active synchronizing control asis provided by synchronizing matrix 1430-3 of Fig. 3, and in addition provides an inhibiting signal of the type utilized in matrix 10Q-2 of Fig. 2. The counting pattern which corresponds to Fig. 4 is illustrated in Fig. 4a.

By reference to Fig. 4 it will be noted that the active synchronizing control is mechanized in a dilferent manner from that shown in Fig. 3. 'The algebraic expression is the same, namely,

In Fig. 3 matrix 100-3 is shown as providing only the or function (D-i-S), this signal then being supplied to count control matrix 210-3 Where it is combined with tre clock pulse Cp in a conventional and circuit. In Fig. 4, however, the entire function is shown as being provided by matrix 100-4, utilizing an and-or circuit of the type described in copending U. S. patent application Serial No. 327,133 for Diode, Pulse-Gating Circuits, by R. D. Forrest, led December 20, 1952. It will be noted that this mechanization, which is equivalent to that shown in Fig. 3, requires only a single diode more than the normal mechanization of the counter in the absence of synchronizing means.

The inhibiting signal provided by matrix 10S-4 is applied to the O-input of ip-op D, the specic mechanization being:

This mechanization has the eect of inhibiting the change of flip-hop D from 1 to 0, upon the occurrence of a synchronizing signal S. By referring to the normal counting sequence shown in Table lli above it may be noted that -this mechanization causes count 1 to repeat, count 6 to advance to count 15, count 9 to advance to count 14, and count 3 to advance to count 6. These altered counting cycles include 1, 7, 1l, and 13 counts, respectively.

The counting pattern of Fig. 4a includes the altered counting cycles of Fig. 3a, plus the four additional altered cycles produced by the inhibiting signal. Accordingly,

possible synchronizing periods for the circuit of Fig. 4i are as follows:

Dcz=3, 18, 33, 48,

Dcr-8, 23, 38, 53,

Dcs=13, 28, 43,

Der: 14, 29, 44,

Synchronous operation of the circuit of Fig. 4 at 16 counts may be achieved and maintained despite the fact that a possible synchronizing period, 48 counts, is a. multiple of the desired period. The reason for this is that, in order to maintain synchronous operation at 48 counts, a synchronizing signal must coincide with count 8 for producing the 3count altered counting cycle. If

another synchronizing signal occurs 16 counts later it will i coincide with count 6, initiating the 7-count altered counting cycle. Two periods of 16 counts later the synchronizing signal will coincide with count 1, and synchronous operation at 16 counts is thereby initiated.

A particular advantage of utilizing a counting pattern according to Fig. 4a is that only the 1A and 0D ip-op inputs would be affected. It would therefore be possible to utilize ashifting register of any desired type in lieu of flip-flops A, B, and C, for example, .a magnetic drum shifting register might be utilized.

The time required for synchronous operation to be attained may if desired be minimized by controlling a greater number of flip-flop input circuits. For example, in the circuit of Fig. 4 the maximum number of synchronizing periods required for attaining synchronous operation can be reduced from 6 to 3 by including as additional circuit modifications:

The application of the invention is not limited to the Johnson counters described in the preceding discussion, but also extends to many other types of counters, as for example, a binary counter. This type of application is illustrated in Fig. 5 wherein a synchronizing matrix -5 is utilized to control the operation of a binary counter 200-5, normally having scale-of-l6 operation under the control of a count control matrix 210-5, to operate as a scale-of-17 counter.

The basic counter circuit of Fig. 5 is described in copending U. S. patent application Serial No. 245,860 for High-Speed Flip-Flop Counters, by Eldred C. Nelson, iiled September 10, 1951. The normal mechanization of matrix 210-5 to provide scale-of-16 operation is defined bythe equations:

1D=0D=A.B.C.Cp The natural counting cycle of counter 200-5 defined by these equations is indicated in Table IV below.

Table IV Count D C B A 0 0 O 0 0 0 0 0 1 0 0 1 0 1 0 0 l O 0 l 1 0 l 1 1 0 0 1 0 0 1 0 l 1 0 1 1 1 0 1 l 0 1 l 1 1 1 l Y one, ofL the counts,

t1 InTreferringtoTable IV it will be noted that although there are several count progressions whereQonly ore' 'ip` A flop changes state between V one:coim,t:and the succeeding count, for none Vof thesei'sthatfzparticular change of that particular flip-hop unique; i For VVexample, in progressing from count 14 to cour-xt lS onlyjlip-iiopfA changes state, the change being fromO'tol, Vbut fl-ipgiiop A also changes from 0 to 1 at seven'otherpoirits inthef-natural counting cycle. In advancing irons,fcount7,:tol count 8 nip-flop D changes vfrom 0 to, lfand this ,isY vthe Vonly point in the natural counting cycle .where Bipflop D makes this change, but inhibitingthis change of' Bip-liep D would.

not cause count 7 to. repeat but instead, wouldcause count 7 tov advance to Ycount 01 From these` considerations'it is. apparentY thatY it is necessary toutilize more than asinglega'ting element to provide a repetition of Thpccifi' mechanization of matrix 100-5 isdefinedY by` Vthe equation zV This mechanization alters the natural counting cycle only Vby, producing a; repetition ofVV count O when signaly S coincides therewith.

vTwotypes odiiculties in obtaining initial synchronism of a counter have already been pointed out. nection with Fig. 2 there'h'as been. illustrated the dificulty whichv may arise wherethe desired synchronizing periodlisa submultiple of another possible synchronizing u period.V Inconnection with Fig. 3 it has also been pointed out thatgadiiculty may arise Where there is a common Y factor between the desired count Dc and the natural.

counting cycles corresponding to a particular mechanizai tion of the synchronizing matrix. In order to insure that the desired precession will be Yobtained the operation'of the. circuit may 'be traced with respect to the possible coincidence of. the first synchronizing signal S with any one of the'zcountslof. the natural counting cycle.

In.the foregoing discussion it has beenV shown thata counter synchronizing circuit may be simply mechanized by permitting the counter to precess during an initial operating period. It has also..been shown that the operation of a counter may be synchronized in a cycle including a number of counts different from the natural count; for example, 2"-i-1 counts, where the counter includes n stages and the` natural count is 2n. specific embodiments haveV shown how j a scale-of-S counter may be operated at 9 counts, a scale-of-l counter a-t 17 counts, a scale-of-lS counter at 16 counts, and a scale-of-lS counter at 14 counts. It has been demon- In constrated that the synchronizing circuits of the present invention not only simplify the circuit mechanization, but Y also minimize the loading etect of the synchronizing circuit upon the counter circuit. Y,

It may be noted that, as a general rule, the synchronizing circuits of the present invention may be most simply mechanized when used in combination with a counterv which includes in its natural counting sequence at leastV one change of count which involves aY changein only .one V Iohnsoncounters, as described in therpreceding discus-V sion, butY also is characteristic. of other counters as, for

Y 12 i example, counters mechanized in the Gray or reflectedf binary code. This code is described in U. S.YPatent No.V 2,538,615 entitled Decoder vfor Reiec'ted Binary CodesV Lby Robert L. Carbrey, issued] anuary 16, 1951./I

Although inY some applications the count.V signals orVV pulses Cpmay themselves be periodic, recurring atreve'nly-` spaced time intervals, this is not` a'n'fessentialV limitation.

of the invention. It is essential, however, that synchronizing signals Shave a period corresponding to a xed numf. ber ofsignals Cp. V

`It may be noted that in the preceding discussionsignal S has been considered as a Voltage-level signal' which! exists during a particular count, including the' terminalV portion of the count when a countpulseor signal Cpl is Yapplied for producing the succeeding count.V VIt is posf.

sible, however, for both signals S andV Cp to be voltage-l level signals, or for both to be pulses. Inkeeping with the present'invention any type of circuit mechanization may be employed so longias signal Cp` aloneproduces the next count of the natural cycle, and the additional oc currence of signal VS during aA particular count either- Will' or will not produce an altered counting cycle, according to the particular mechanization. n

It will be apparent to those skilled in'the'art that the .method and circuits of the present invention-have a wide Y variety of applicationsV and are not limited to la particulartype of counter or to a counter of any particular normal counting capacity; Y

What is claimed as new is:Y

V1. A synchronizing circuit forsynchronizing a counter at an altered count, the counter comprising a plurality of iiip-op stages each having a pair of input circuits controlled through separate gating circuits, the counter being normally operative in response to count pulses to l Vproduce a natural counting cycle including a l'lrstv number of counts; said synchronizing circuit being responsive to applied. synchronizing signalsfor establishing and main.- ta-ining operation of the counter in a'V counting cycle' including a second number of counts, the period of said' synchronizing signals being measurable by'. a, number of Vcount pulse periods equal to said second. number, sardiY second number being diierent from said first number. said synchronizing circuit comprising: first means coupled to at least one flip-hop input circuit and responsive to successive synchronizing signals for Vactuating the counter to 'precess until one synchronizing signal coincides with apredetermined countv ofthey natural cycle;and.'seco`nd means coupled to at least one flip-flop., input-circuit and:`V responsive to saidone synchronizing. signal forv actuating the counter to initiate an altered counting cycle, the num; ber of counts of said .altered cycle being less. than, said'.

second number by anintegral multiple of said. firstnumf ber. n i

V2. The synchronizing circuit defined in'claim l wherein said first number of counts is` 2N, saidrcounter comprises N flip-flop stages, and said secondnumber.of. counts,'is ZN-l-l, saidv second means being responsive tosaid one, synchronizing sig-nal for. actuating the counter` tov repeat said predetermined count.

3. The circuit defined in claim means includes means for applying an inhibiting signalV to at least one flip-flop input circuit.

4. The synchronizing circuit defined in claim 1 wherein said second means includes meas for applying an active synchronizing control to at least one'flip-op input circuit.;

5. In combination, an electronic counter circuit having a natural counting cycle and a synchronizing matrix opcrable to control said counter circuit in a desired counting cycle diierent from said natural cycle; said counter circuit comprlslng a counting control matrix anda plurality A0i bistable elements and including means for applying count pulses, representing countable-vevents, for producing'- successive counts of the natural cycle, said counter being 5 also actuable during a predeterminedA count to produce analtered counting cycle; saidsynchronizing'matrixcorn i prising atleast one gating element and. including means 1 wherein said second` for applying periodic synchronizing signals, having a period measurable in terms of countable events and different from the natural period of the counter, said matrix being responsive to said synchronizing signals for actuating the counter to produce said altered counting cycle when coincidence between one of said synchronizing sig nals and said predetermined count is achieved.

6. In combination, an electronic counter circuit having a natural counting cycle and a synchronizing matrix operable to control said counter circuit in a desired counting cycle different from said natural cycle; said counter circuit comprising a counting control matrix and a plurality of bistable elements and including means for applying count pulses, representing countable events, for producing successive counts of the natural cycle, said counter being also actuable during a predetermined count to produce an altered counting cycle; said synchronizing matrix comprising at least one gating element and including means for applying periodic synchronizing signals, having a period measurable in terms of countable events and diierent from the natural period of the counter, said matrix being operable to apply said synchronizing signals to the counter for producing coincidence of successive synchronizing signals with progressively different counts of the counter.

7. The synchronizing circuit dened in claim l wherein said first numberof counts corresponds to 15 counts and said second number of counts corresponds to 14 counts.

8. The synchronizing circuit defined in claim 1 wherein said irst number of counts corresponds to l5 counts and said second number of counts corresponds to 16 counts.

9. The synchronizing circuit defined in claim 2 wherein N is equal to 3.

10. The synchronizing circuit defined in claim 2 wherein N is equal to 4.

References Cited in the n'le of this patent UNITED STATES PATENTS 2,504,354 Roschke Apr. 18, 1950 2,527,638 Kreer et al. Oct. 3l, 1950 2,546,316 Peterson Mar. 27, 1951 2,680,195 Thompson .lune 1, 1954 

